The present invention relates to a method of manufacturing semiconductor devices having high reliability. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices with feature dimensions in the deep sub-micron regime.
Various issues arise in attempting to satisfy the ever increasing demands for miniaturization as the design rules plunge into the deep sub-micron regime. For example, it is extremely difficult to deposit high density dielectric layers, such as silicon nitride, with uniform film quality and deposition rate control so that they may effectively function as an etch stop layer without damage to an underlining gate stack or metal silicide layers, particularly in manufacturing non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. Adverting to FIG. 1, a typical single transistor flash EEPROM cell is schematically illustrated and comprises substrate 10, source region 11 and drain region 12 separated by a channel 13. A tunnel oxide 14 insulates substrate 10 from floating gate electrode 15 which, in turn, is insulated from control gate 16 by integrate or interpoly dielectric 17 typically having a three layer structure of silicon dioxide, silicon nitride and silicon dioxide commonly referred to as ONO. Floating gate 15 and control gate 16 are typically formed of doped polysilicon. A layer of oxide 18 is then grown or deposited with subsequent processing to form sidewall spacers. Such flash EEPROM devices offer many advantages; however, reliability issues arise, particularly as dimensions are scaled into the deep submicron regime.
In fabricating various EEPROM devices, as the gate width is scaled down to about 0.18 micron and under, etch selectivity of the silicon nitride etch stop layer with respect to an overlying oxide layer, such as a boron-phosphorus-silicate glass (BPSG), becomes more critical. In accordance with conventional practices, the as-deposited density of a silicon nitride etch stop layer, e.g., by plasma enhanced chemical vapor deposition (PECVD), is typically no greater than about 2.7 g/cm3. A BPSG layer is deposited thereover and etching is conducted to form contact holes to underlying source/drain regions with metal silicide layers thereon, as well as contacts to gate structures. In accordance with conventional practices, the etch selectivity of the silicon nitride layer with respect to the overlying BPSG is about {fraction (1/7)} to about xe2x85x9 Such etch selectivity becomes problematic as micro-miniaturization increases resulting in damage to the metal silicide layers on the gate stack and on the source/drain regions upon etching contact holes.
Accordingly, there exists a need for methodology enabling the manufacture of semiconductor devices with improved reliability, particularly semiconductor devices containing typical MOS transistors as well as flash memory devices, such as EEPROMs. There exists a particular need for methodology enabling the deposition of dielectric layers, such as silicon nitride, with higher density, improved film quality and greater etch selectivity with respect to an overlying oxide layer.
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability.
Another advantage of the present invention is a method of manufacturing flash memory semiconductor devices with high density silicon nitride etch stop layers having increased etch selectivity with respect to an overlying oxide layer.
Additional advantages and other features of the resent invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising depositing a layer of silicon nitride over a semiconductor substrate; and laser thermal annealing the layer of silicon nitride to increase its density.
Embodiments of the present invention comprise forming a non-volatile semiconductor device with metal silicide layers on the gate stack and on associated source/drain regions, depositing a silicon nitride layer, as by PECVD, over the non-volatile device, laser thermal annealing by impinging a pulsed laser light beam on an exposed surface of the silicon nitride layer at a radiant fluence of about 0.163 to about 0.229 joules/cm2 in N2 flowing at a rate of about 200 to about 2000 sccm, thereby elevating the temperature of the silicon nitride layer to about 600xc2x0 C. to about 850xc2x0 C. As a result of laser thermal annealing, the density of the silicon nitride layer is increased from an initial value of no greater than about 2.7 g/cm3, to a density of about 2.75 to about 2.79 g/cm3. An oxide layer is then deposited, such as a BPSG layer, and holes are etched through the BPSG layer stopping at the silicon nitride layer to form contact openings to the gate stack and/or source/drain regions. Laser thermal annealing advantageously increases the etch selectivity of the silicon nitride layer with respect to the subsequent deposited oxide layer as, for example, from an as deposited value of about {fraction (1/7)} to about xe2x85x9 to a value of about {fraction (1/12)} to about {fraction (1/14)}. Such improved etch selectivity prevents damage to the underlying metal silicide layers on the gate stack and associated source/drain regions, thereby improving device reliability, particularly as dimensions are reduced to the sub-micron regime, such as a gate width of about 0.18 micron or less.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.